In a design system for hardware, in order to facilitate extraction and coding of registers in hardware design, PTL 1 discloses, for example: extracting hardware registers from an abstract message sequence between a software model and a hardware model, and presenting the extracted hardware registers; customizing an address and a bit field of each hardware register thus extracted; integrating multiple registers with respect to a group of the extracted hardware registers, and tiering the group of extracted hardware registers; and generating a specification of the group of hardware registers thus customized.
Citation List
Patent Literature
    PTL 1: Japanese Patent Application Laid-Open Publication No. 2005-327192